1. Field of the Invention
The present invention relates to a semiconductor memory circuit which contains therein at least a bias voltage generator for producing a bias voltage of a predetermined level within a range within a power source level and a ground level.
Note: The term "bias voltage" is used in a variety of electronic fields but, in the present invention, this term is used to denote a voltage to be appled to a control gate of each memory cell. To be specific, in a semiconductor memory of an electrically erasable programmable read-only memory (EEPROM) type, each of the memory cells is comprised of a programming transistor and a selecting transistor connected in series. In the EEPROM, the control gate of each programming transistor is applied with a bias voltage having a level in a range between a power source (V.sub.cc) level and a ground level, for example, 2 to 3 V, when the EEPROM is operated under a read mode, as will be clarified hereinafter.
2. Description of the Related Art
In general, the prior art bias voltage generator, comprised of at least one field effect transistor (FET) pair, is used to produce the desired bias voltage by flowing a certain current through the FET's. In other words, the prior art bias voltage generator cannot produce the desired bias voltage without having a current supplied thereto. Therefore, the prior art bias voltage generator is disadvantageous from the view point of power consumption in the semiconductor memory circuit.